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Altera_Forum
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10 years ago

Stratix V pin I/O delays

Hi I am currently trying to build a board with some DDR3 memory on, and for that I need the PIN I/O delays so I can do external Deskewing. but I can't figure out how to generate this pin de...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

I am looking for the internal delay of each pin. in Xilinx I can just draw a list.

This should be a constant for that version of my chip.

I don't see why I need to configure any design for this?