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Altera_Forum
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13 years ago

Stratix IV PLL limits

Hi: I have a 2 fpga stratix iv board and I want to generate a 1 MHz synchronous clock in both. When I use the PLL, quartus refuses to let me give a clock slower than 5MHz to the PLL. How c...
Altera_Forum's avatar
Altera_Forum
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13 years ago

The basic answer is 'maybe', but there are several other things to consider.

(i) Where is the master clock sourced from?

(ii) What is the frequency?

(iii) Is the clock balanced between the two FPGAs? By this, I am asking whether the trace lengths are the same so that the time it takes the clock to arrive at each FPGA is the same

(iv) When you ask if the clocks will be in sync, what you are really asking is whether the clocks will be in phase. There will always be some phase difference - how much are you able to tolerate?

If you could explain exactly what you are trying to do, that would help.