Honored Contributor
Honored ContributorHello Axel,
I don't know, if I'll have the time to follow the problem in detail. First I have to continue some customer projects. I started to compare gate level implementation, but found it somewhat annoying. I didn't see an explicite bug yet. Basically, all transitions from illegal states must be considered undefined, unless you don't have a "safe" FSM. At some of these illegal states, the state machine could be stuck forever, if accidently reaching it. As minimal reason, a timing violation on any input signal could cause this situation. I expect the implementation differences to show only for illegal states, if this guess is true, you can't say one implementation is right and the other wrong. They're all correct as long as the defined behaviour is exactly implemented. I didn't pay much attention to the FSM viewer, I probably would have missed a bug here. By the way: Safe FSM option had been introduced with Quartus with V 7.0, I believe, that's rather fresh. Before the option was included, there was a good chance that Quartus would optimize respectively eliminate any try to implement safe FSM logic. Apparently, FSM support has been neglected for a period of time. Regards, Frank