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Altera_Forum
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18 years ago

Strange State Machine Compilation - Compiler Bug?

Hi @all, I'm using Quartus 7.2 and I'm wondering about the implementation of FSMs which are coded with one segment (process) style and havn't a default assignment for the state variable/signal....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello,

You need a "feedback in datapath" anyway to hold a present state. Either as input to an "IF" MUX, or as selector for a "CASE" MUX. If you imagine that the compiler merges the two levels (if and case) at the state register input when creating the "initial netlist", the logic would be identical for both cases.

Regards,

Frank