Strange State Machine Compilation - Compiler Bug?

Hello Frank,

thanks for your fast reply.

You aren't right. I had forgotten that it only happens in greater FSMs. In the following example I have added one signal to the state transition conditions.

With else:

14 LEs, 11 Registers, fmax: 556 Mhz

Without else:

15 LEs, 11 Registers, fmax: 373 Mhz

I use identical synthesis and fitter options. (safe state machine encoding is off; standard one-hot encoding)

You say "I would expect the two cases to produce identical gate level netlists, cause the compiler is free to minimize the logic as far as possible." - I also expect the same. But it doesn't result in the same Post-Mapping and thats the reason for this thread...

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity performancetest_1_fsm2conditions is
	port(
		clk              : in std_logic;
		reset            : in std_logic;
		trafficLight_ena : in std_logic;
		input            : in std_logic;
		output           : out std_logic_vector(1 downto 0)
	);
end entity performancetest_1_fsm2conditions;
architecture performancetest of performancetest_1_fsm2conditions is
	type STATES is (init, green, yellow, red);
	signal state : STATES;
	signal reset_timer : std_logic;
	signal timer_max   : std_logic;
	
component timer
	port(
		clk         : in std_logic;
		reset       : in std_logic;
		reset_timer : in std_logic;
		timer_max   : out std_logic
	);
end component;
begin
timer1:timer 
	port map (
	clk         => clk,
	reset       => reset,
	reset_timer => reset_timer,
	timer_max   => timer_max
	);
process(clk,reset)
	variable reset_timer_var : std_logic;
begin
	if reset = '1' then
		output <= "00";
		reset_timer_var := '0';
		state <= init;
	elsif clk'event and clk = '1' then
		reset_timer_var := '0';
		if trafficLight_ena = '0' then
			reset_timer_var := '1';
			state <= init;
		else
			case state is
				when init =>
					output <= "00";
					if trafficLight_ena = '1' then
						reset_timer_var := '1';
						state <= red;
					end if;
				when green =>
					output <= "01";
					if timer_max = '1' and input = '0' then
						state <= yellow;
					end if;
				when yellow =>
					output <= "10";
					reset_timer_var := '1';
					state <= red;
				when red =>
					output <= "11";
					if timer_max = '1' and input = '1' then
						reset_timer_var := '1';
						state <= green;
					end if;
			end case;
		end if;
		reset_timer <= reset_timer_var;
	end if;
end process;
end performancetest;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity timer is
	port(
		clk         : in std_logic;
		reset       : in std_logic;
		reset_timer : in std_logic;
		timer_max   : out std_logic
	);
end entity timer;
architecture timercnt of timer is
begin
timecnt:process(clk, reset)
	variable timer : integer range 0 to 7;
begin
	if reset = '1' then
		timer := 0;
	elsif clk'event and clk = '1' then
		if reset_timer = '1' then
			timer := 0;
		else
			timer := timer + 1;
		end if;
		if timer = 7 then
			timer_max <= '1';
		else 
			timer_max <= '0';
		end if;
	end if;
	
end process;
end timercnt;