Honored Contributor
Honored ContributorHello Axel,
I can't verify resource usage differences using or not using the else statements. I guess the last else should be state <= red, but that also makes no significant difference. Could it be that additional non-default synthesis settings are in effect in your dessign? Also, some defaults may depend on used device, which is unknown. In constrast, when using the "safe" FSM coding style, the design needs a few more resources, but two LE less when the else statements are included, actually no big effect. If anything causes the reported behaviour, it isn't apparently in the shown code. When not coding a safe FSM, I would expect the two cases to produce identical gate level netlists, cause the compiler is free to minimize the logic as far as possible. As an example, before Altera introduced the "safe" option with Quartus, an additional others case, causing a transition to the init state always had been kicked out during synthesis. Regards, Frank