Strange Quartus warning with LVDS pin

Hello,

I get a fitter warning regarding an automaticly placed inverted differential input pin:

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Warning: DDIO pin "ADC_LVD[8](n)" cannot be placed at its location "PIN 176" because that location cannot directly feed the data-in ports of the DDIO input registers.

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But in the Pin-Out File, the pin has been correctly assigned. The warning already existed with Quartus V7.2 as a Critical Warning and continues with V8.1 as a regular warning.

The online help gives an explanations that is obviously wrong in the present case.

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CAUSE: The specified DDIO pin has been assigned to a location intended for clock I/O and must be assigned a different location.

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In Pin Planner tool, the differential pair also shows normal. The device is EP3C16Q240.

Anyone experienced a similar behaviour? Is it a Quartus bug?

Regards,

Frank

P.S.: I remember, that I got a similar warning with a positive LVDS pin in another design. As PIN 176, the said pin also had a CDPCLK additional function, which makes me think, it's a meaningless warning related to this pin function. The LVDS operation has been checked OK with the recent design.