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Altera_Forum's avatar
Altera_Forum
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14 years ago

Strange compiltaion

Hi,

I have an strange problem so I need help because I don’t know what happen.

The first time that project have been compiled no problems ,(total logic elements 719/1270 (57%) with device EPM1270

but when I add to the project one simple sentence, the device need a lot of logic elements (total logic elements 2018/1270 (159%) with device EPM1270

always @ (posedge clk_i)//wb_clk_i

begin

wb_ack_o <=#Tp (cs_ack2 & (~cs_ack3));

end

What can I do to solve this?

Regards,

Javi

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    #Tp means the assignment is to be made Tp time units after the clock edge.

    This is probably synthesized through a delay chain built with a lot of cascaded LE.

    The# must be used only used in test bench for simulation, not in hardware description.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks for the advice

    I have supresed the# Tp in the sentence, however the compilation is given the same problem..:(
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The more probable explanation is that wb_ack_o feeds a lot logic that was previously eliminated during synthesis because of the undefined input.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I have build my proyect in bigger device, EPM2210, and I have a new different problem. The total logic elements of EPM2210 is 2210, and for my proyect I need 2042 (92% of EPM2210), however the result of the compiltaion in a error.

    error: final fitting attempt was unsuccessful

    info: failed to route the following 15 signal(s)

    info: signal "can_top:component_2|can_bsp:i_can_bsp|selector1~5"

    info: signal "can_top:component_2|can_btl:i_can_btl|sampled_bit"

    info: signal "can_top:component_2|can_bsp:i_can_bsp|can_fifo:i_can_fifo|always1~0"

    info: signal "can_top:component_2|can_bsp:i_can_bsp|error_frame_ended~1"

    info: signal "can_top:component_2|can_bsp:i_can_bsp|bus_free_cnt[2]"

    info: signal "can_top:component_2|can_bsp:i_can_bsp|can_fifo:i_can_fifo|fifo~893"

    info: signal "can_top:component_2|can_bsp:i_can_bsp|can_fifo:i_can_fifo|fifo_cnt[6]"

    info: signal "can_top:component_2|can_bsp:i_can_bsp|always21~0"

    info: signal "can_top:component_2|can_bsp:i_can_bsp|crc_in[11]"

    info: signal "can_top:component_2|can_bsp:i_can_bsp|can_fifo:i_can_fifo|fifo~421"

    info: signal "can_top:component_2|can_bsp:i_can_bsp|data_len[1]"

    info: signal "can_top:component_2|can_bsp:i_can_bsp|can_fifo:i_can_fifo|fifo~525"

    info: signal "can_top:component_2|can_bsp:i_can_bsp|can_fifo:i_can_fifo|fifo~886"

    info: signal "can_top:component_2|can_bsp:i_can_bsp|can_fifo:i_can_fifo|fifo~193"

    info: signal "can_top:component_2|can_registers:i_can_registers|can_register_asyn:mode_reg_basic|data_out[0]"

    info: cannot fit design in device -- following 16 routing resource(s) needed by more than one signal during the last fitting attempt

    info: routing resource r4 (x10_y8, i7)

    info: routing resource r4 (x12_y10, i13)

    info: routing resource r4 (x13_y8, i5)

    info: routing resource r4 (x16_y5, i15)

    info: routing resource r4 (x17_y6, i13)

    info: routing resource r4 (x20_y6, i4)

    info: routing resource r4 (x20_y8, i5)

    info: routing resource r4 (x20_y8, i15)

    info: routing resource c4 (x19_y0, i20)

    info: routing resource c4 (x19_y4, i12)

    info: routing resource c4 (x19_y5, i11)

    info: routing resource c4 (x20_y5, i13)

    info: routing resource lab local interconnect (x6_y6, i16)

    info: routing resource lab local interconnect (x19_y9, i19)

    info: routing resource lab internal resource (x8_y4, i4)

    info: routing resource logic cell input (data4) (x19_y9_n7, i39)

    error: quartus ii fitter was unsuccessful. 2 errors, 3 warnings

    error: quartus ii full compilation was unsuccessful. 4 errors, 34 warnings

    I dont know what happened, because the EPM2210 have more nº of total logic elements than my requeriments. Some suggestion to solve this?

    Regards

    Javi
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    the answers are in the error report. you have enough logic elements but not enough routing resources to connect all of the pieces

    you can revisit the code and try and optimize it, but FIFOs in a MAXII seems a bit optimistic
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks for the advice

    My project need a little fito, is CAN controller. How I revisit the code and optimize it? I dont know how to do it, you can suggest me some way, some options in quartus...

    Regards

    Javi
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    How large is your fifo? thepancake is correct. FIFOs in a MAXII is a bit optimistic unless it is VERY shallow.