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Altera_Forum's avatar
Altera_Forum
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14 years ago

Strange compiler behaviour

Hello,

I'm experiencing a strange behavior of the quartus 10.1 compiler when I'm using a block design file as top level entity.

I created a small test project with only one counter (see the attached screen shot) and the compiler report tells me that 0 logic elements are used. Can anyone explain this to me?

I attached screen shots of the block design and the compilation report

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Maybe an error in your HDL Code.

    During Analysis and Synthesis, your "Counter" will be optimized.

    If you make an error, like (Reset is olways active or Count Enable is always inactive) the Synthesis Tool will solve your Design.

    In this case,

    no logic ressources will be used and the output pins are always zero
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    When you break the output bus, you made a mistake. There are no outputs in the circuit.