Strange comparator behavior

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I have a simple comparator project which compares two 2-bit words. I wrote a code, but time diagrams show some strange behavior:

library IEEE;
use IEEE.std_logic_1164.all;
entity cmp is
port ( x0, x1, y0, y1, L, E, G : in std_logic;
Lo,Eo,Go : out std_logic);
end cmp;
architecture behav of cmp is
signal LEG: std_logic_vector(0 to 2);
begin
process (x0,x1,y0,y1,L,E,G)
begin
    if x1>y1 then LEG<="001";
    elsif x1<y1 then LEG<="100";
    else
        if x0>y0 then LEG<="001";
        elsif x0<y0 then LEG<="100";
        else 
            if G='1' then LEG<="001";
            elsif L='1' then LEG<="100";
            else LEG<="010";
            end if;
        end if;
    end if;
end process;
Lo<=LEG(0); Eo<=LEG(1); Go<=LEG(2);
end behav;

https://alteraforum.com/forum/attachment.php?attachmentid=13620&stc=1

I looked through my code but didn't find a mistake which makes for example "Go" output to fall and rise near the 50th ns. Is it my mistake or maybe Max+Plus II (v.10.0) bug?

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I guess you are doing a gate-level simulation where real delays in silicon come in to play.

Not all paths from input to output have the same levels of logic and as a result you get these glitches.

Now you did build a truly asynchronous circuit, and these are inherently prone to race and glitch conditions.

Google asynchronous race glitch (https://www.google.be/search?client=opera&q=asynchronous+race+glitch&sourceid=opera&ie=utf-8&oe=utf-8) and you will find lots of info to learn all about it.