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Altera_Forum
Honored Contributor
13 years agoI synchronize rd/wr signals using a PLL, it has two outputs and have a speed of 10MHz one of them is conecting at an inversor , the first output is used by the rd signal and the other one is used by the wr signal.
The two FIFOs are using because while the first is reading the another is writing so there aren't data's lost this design is only one idea I don't have experience in FIFO's memories so if you have ideas you can tell me, the main goal is storing 1024 bits in a memory, i have 8 input bits in parallel with a speed of 100msps, the dates must be storing in a vector Thanks so much!!!