Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

std_logic_vector won't accept certain values

I was asked to design a simple can dispensing machine using VHDL.I have an input called CoinIn and is defined as an std_logic_vector(1 downto 0);for some reason, when I try to force it with a "11" it...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thank you very much for your reply.

I'm not sure I understood - were you able to assign values other than 00 and 01 to CoinIn?

Are you suggesting that the problem is caused because I used force rather than a TB?

About the counter - thanks for explaining. How would you suggest implementing it then?

Will moving the counting feature under the rising_edge condition work?