std_logic_vector won't accept certain values

Instead of using force as your testbench, I highly suggest writing a VHDL testbench for you simulation. It will teach you more and give you more control.

I have run your macro and code, and I also dont quite understand (I never use the force command, and I dont know anyone that does)

A couple of notes on your code:

You count signal will be created with as a latch as it is not assigned in every state.

Also, you cannot implement the count signal inthe asynchronous state machine process as you have a subtractor in there. The code as it is will not match the real hardware - to get real hardware count must be in the sensitivity list, and you will notice you will get yourself into an infinite loop, as count will constantly try and subtract 2 from itself (as will occur in real hardware). You cannot have counters in asynchronous processes, they must be synchronous.