Altera_ForumHonored Contributor11 years agostd_logic_vector won't accept certain values I was asked to design a simple can dispensing machine using VHDL.I have an input called CoinIn and is defined as an std_logic_vector(1 downto 0);for some reason, when I try to force it with a "11" it...Show More
Altera_ForumHonored Contributor11 years agoThe problem is in your code - without the code, we cannot help.
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