state of FPGA pins before bitmap takes effect

I look at Cyclone IV device manual.

http://www.altera.com/literature/hb/cyclone-iv/cyclone4-handbook.pdf

It says this:

I/O Pins Remain Tri-stated During Power-Up

The output buffers of Cyclone IV devices are turned off during system power up or

power down. Cyclone IV devices do not drive out until the device is configured and

working in recommended operating conditions. The I/O pins are tri-stated until the

device enters user mode.

So I would conclude that we cannot define/ control the logic high/low state of FPGA output pins before bitmap takes effect.

Comments/ corrections are welcome.