state of FPGA pins before bitmap takes effect

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Is there a way to define/ control the logic high/low state of FPGA output pins in this time interval? I mean, to define/ control from FPGA chip itself, not from other components on the board.

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It depends on the FPGA.

Some FPGAs have an IO_PULLUP pin that can be used to define whether weak pull-ups are enabled or not during power on, i.e., you have a "global" option, rather than a per pin option.

Generally I use pull-up or pull-down resistors on control signals that I want to guarantee have a particular state when the FPGA is not configured.

Cheers,

Dave