State Machine Wizard

The "StateX=N" is using N as the bit number. Quartus will by default decompose state machines and reencode them as one-hot, as this form is much more resource efficient when implementing in the FPGA. You can direct Quartus not to do this by adding the syn_encoding attribute to the Verilog source on the state machine definition. Or to influence all state machines, in the .qsf file use the state_machine_processing directive as in:

https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#logicops/logicops/def_smp_process_type.htm

The default is 'auto', where Quartus will decide the 'best' encoding that meets timing and uses minimal resources. Choose 'user-encoded' if you want quartus to leave as is.