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Altera_Forum's avatar
Altera_Forum
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9 years ago

State Machine Viewer

Hi, I designed a state machine in my verilog codes. I evaluate it in the DE2-115 board, and everything looks good. When I opened the state machine viewer in the Quartus II 12.0, however, it sho...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Don't know about that, but why do you mix blocking (=) and non-blocking (<=) assignments in your code?

That is really bad coding practice and can lead to numerous subtle simulation vs implementation errors.

I would recommend you change all the blocking to non-blocking assignments.

It may also be why the tool can't detect the state transitions, but I'm just guessing on that.