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Altera_Forum's avatar
Altera_Forum
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13 years ago

State Machine Names in ModelSim

Hi All, I have a question about state machines in ModelSim. When I simulate a Verilog design that includes a state machine and add the state register to the wave window in modelsim, it shows ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

AFAIK, the only way to achieve that is to use System Verilog instead of plain Verilog and use "enum" types for the state.

Example:

enum { S_FIRST, S_SECOND, S_THIRD } state;