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Altera_Forum
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15 years ago

State Machine File Tutorial??

Hi, I'm new to using State Machine Files for design. Creating the FSM was easy, but I want to compile and implement. I'm using Quartus 9.0 with DE2 Boards. I have questions: 1) Is there...
Altera_Forum's avatar
Altera_Forum
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15 years ago

The Quartus II software saves the state machine diagram as a State Machine File (.smf). After defining the state machine logic, you can create a Verilog HDL or VHDL design file by clicking the Generate HDL File icon. You can then instantiate the state machine in your design using any design entry language.