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Altera_Forum
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13 years ago

State Machine - CASE\WHEN and glitches

Hi everyone, I'm a bit lost and I need your help. In my design I'm using a state machine I coded in VHDL to control a small ALU for floating point operations. The state machine is divided ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

MAC_Advance shows just regular behaviour of a FSM design. The "glitches" occur only shortly after clock edges and are ignored by any clock synchronous logic fed by the signal. If you are using the signal in an asynchronous design, it has to be registered to the FSM clock.

Problems like the present are a reason why many people prefer a simple FSM topology with one clocked process, where all signals are registered.