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Altera_Forum's avatar
Altera_Forum
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13 years ago

State Machine - CASE\WHEN and glitches

Hi everyone, I'm a bit lost and I need your help. In my design I'm using a state machine I coded in VHDL to control a small ALU for floating point operations. The state machine is divided ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I will assume you passed timing.

Before anything else I note you have put default values before case statement but then you repeated some default assignments e.g.

WHEN 6 => MAC_Advance <='0';

yet MAC_Advance is on default of '0' anyway. You need not put this line but it does not answer your issue. I am just thinking you might be misunderstanding this default issue. In fact you can remove all assignments of '0' when already in default.