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Altera_Forum's avatar
Altera_Forum
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12 years ago

STAP steering vector generation

hello everyone I have run one of DSP builder's reference designs named STAP steering vector generation, the dsp builder made a vhdl code. I changed the inputs to constant signals. and just a clock...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

thank you for your quick answer

but what do you mean by removing all the logic? I defined that input signals whith the same name they had before this .