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Altera_Forum
Honored Contributor
Honored Contributor[STA] Timing Constraints for synchronizers
Hi All, What timing constraints should be applied for the synchronizers? 1) false path from a clock pin of the first flop to D-pin of the second/last flop 2) what about ...
Altera_ForumHonored Contributor
Honored Contributorno, a false path will override a max delay. A false path will probably be fine, but theres no guarantee the placer wont put the endpoints at opposite corners of the chip. Using a max delay (with a very relaxed constraint) should ensure they're reasonably close.
