Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

[STA] Timing Constraints for synchronizers

Hi All, What timing constraints should be applied for the synchronizers? 1) false path from a clock pin of the first flop to D-pin of the second/last flop 2) what about ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

no, a false path will override a max delay. A false path will probably be fine, but theres no guarantee the placer wont put the endpoints at opposite corners of the chip. Using a max delay (with a very relaxed constraint) should ensure they're reasonably close.