[STA] Timing Constraints for synchronizers

1. You only need the false path between the registers that actually cross the clock domain. Unlike Xilinx, who insist you time everything from pin to pin, making getting the paths correct annoying and a little tedious, Altera have a get_keepers function, that make it easier to fetch objects. Usually its often easier just easier to set a -to or -from for a single end-point rather than both ends.

set_false_path -to [get_keepers */my_ent/cdc_reg_clkB]

2. Multi-cycle paths should only be set on registers that actually have a multicycle path. Synchronisers often do not. Are you talking about some specific design?