SRAM constraints

Please help to constrain the following schema (see picture):

DataOut pin is a positive pulse of 10 ns, WE signal is a negative pulse of 7.5 ns.

External device latches signal from DataOut pin by rising edge of WE pin (like a SRAM).

Relationship between WE and DataOut at the external device side is: tsu = 4.9 ns, th = 0.1 ns.

In my poject I create shifted clock using PLL and create WE signal by "nand" of triggers, latching "enable" signal

with this clock and main clock.

At this time my sdc is:

create_clock -name {ClkIn} -period 10.000 -waveform { 0.000 5.00 } [get_ports {ClkIn}]

derive_pll_clocks

create_generated_clock -name ClkWE -source [get_nets {inst|altpll_component|_clk0}] -duty_cycle 75 -offset 2

set_output_delay -clock [get_clocks {ClkWE}] -max 4.9 [get_ports {DataOut}]

set_output_delay -clock [get_clocks {ClkWE}] -min -0.1 [get_ports {DataOut}]

I do not know how to tell timequest, that WE is generated from two clocks with phase shift set in PLL settings.

Now changing PLL settings does not affect analysis.

Thank you.

Forum Discussion