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Altera_Forum
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16 years ago

SPI Slave and Timing Constraints

I am currently working on a project where we are using a MAX II EPM570-C5N. I am currently working in Quartus on compiling my HDL and fitting it to the part. While working with my constraints, I ha...
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Altera_Forum
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14 years ago

> P.S.: I didn't yet meet a case, where it was necessary to constrain the SPI data lines.

I am surprised and concerned not to. Are constraints considered unnecessary given Cyclone III project with ~5 SPI ports at 20MHz system clock (SPI clock ~5MHz)? Is there something specific about SPI that makes constraints less important? The inference is for MISO and MOSI; I wonder also about the clocks and chip selects.