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Altera_Forum
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16 years ago

SPI Slave and Timing Constraints

I am currently working on a project where we are using a MAX II EPM570-C5N. I am currently working in Quartus on compiling my HDL and fitting it to the part. While working with my constraints, I ha...
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Altera_Forum
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16 years ago

I expect, that you have edge sensitive blocks for both edges in your code. Specifying a duty cycle for the SPI clock gives all necessary information to the timing analyzer in my opinion.

P.S.: I didn't yet meet a case, where it was necessary to constrain the SPI data lines.