Speed up Gate-level simulation

Hi,

Thanks for the replies. For now I am trying to split the design up and test the 3 main components separately. This has a number of advantages in that I can run multiple instances of Modelsim and therefore simulate all three components at once. Each of the 3 broken down designs is considerably smaller as in each case the signals relating to the other two components are removed - only one component is ever operational at any time in the complete design anyway. With Modelsim Altera simulation optimization is not supported, one other idea from Altera support would be to disable signal logging in the wlf file until the time of interest.... I'll let you all know how I get on.