Occasional ContributorSpecific to Logic-lock(chip planner)
Hi,
I have a logic , where I have used 624 9x9 multipliers.
Device used - cyclone V GT( It has 342 DSP with each DSP having three 9x9 multipliers).
Fitter couldn't merge these 9x9 multipliers into a single DSP.It used to fail giving error as overuse of DSPs. So, I used logic lock to fit this Logic by randomly giving width and height( with specific number of DSPs resources).
Now , there was no fitter error .Before doing logic lock clock frequency achieved was 250 Mhz. After logic lock it dropped to 200 Mhz.
When I checked timing analyzer, critical path shown is in internals of lpm_mult IP. Note that I have registered input before passing to multipliers , and the output latency is also 3 clock cycles. So , ideally I should achieve max frequency of multipliers i.e, 300MHz. But it is not even meeting 200 MHz ( I feel it is because of logic lock).
Please answer below queries related to logic lock:
1) What is the correct way to select width and height of logic lock region?Please share some example design/ pdfs which describes how to work with chip planner and logic lock in detail?
2) How to achieve optimum frequency in logic locked region?Is there a way to give timing constraints separately for logic lock region?
Thankyou,
regards,
Yogesh
