Specific to Logic-lock(chip planner)

Hi Yogesh,

I'm so sorry for that, please try what I recommend below and let me know any result you get.

I recommend setting the DSP usage for that module so, please try the following:

• Right-click on the module in the hierarchy and choose Local Node and then Assignment Editor
• once you are there, click on new, and in the row of the new assignment click <new> under Assignment name and select the Maximum DSP block usage.
• Put the expected number of DSP blocks to be used in the value column.
• Finally, select save and compile, and test again your project.

Regarding some documentation in case you still wanted to use logic lock regions, I add the link to a Chip Planner video-training which shows the correct way to create logic lock regions, this starts at minute 19:46.

It is important to mention that packing the DSP's is going to reduce the Fmax.

You will have area reduction or Fmax, but not both.

Setting separate timing constraints for logic lock region is not possible but what you can do is to create a design partition in that specific region and apply different settings to help with timing.

maybe this link can be helpful if you consider to use incremental based timing closure.

Please let me know all question you may have.

Thanks,

-Eliath