Source Synchronous representation in TimeQuest - FPGA is a transmitter

Can you post just the .sdc file?

You need a false path on your output clock path because the tool is looking at this path still as a data path:

set_false_path -to [get_ports ssync_tx_clk_ext]

The false paths you mention you created should be from the data clock (the clock that is driving out data) to ssync_tx_clk_ext, something like this:

set_false_path -setup -rise_from [get_clocks data_clk] -fall_to [get_clocks ssync_tx_clk_ext]

set_false_path -setup -fall_from [get_clocks data_clk] -rise_to [get_clocks ssync_tx_clk_ext]

set_false_path -hold -rise_from [get_clocks data_clk] -rise_to [get_clocks ssync_tx_clk_ext]

set_false_path -hold -fall_from [get_clocks data_clk] -fall_to [get_clocks ssync_tx_clk_ext]

Can you confirm this is how you did your constraints?

#iwork4intel