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Altera_Forum
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9 years ago

Source Synchronous mode in different quartus version

hi, everyone, I have a design using alt_pll Source Synchronous mode, and I make the data input pin "rx" an PLL Compensation assignment. When builded with Quartus 9.1, the "rx" input register...
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Altera_Forum
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9 years ago

I see that sfr_reg[1] is implemented as fast input register in Quartus 9. sfr_reg[0] is however not fed by an input pin and can't be implemented as fast input register. I wonder how the compensation for the common clock is expected to work in this case.

You can make sfr_reg[1] a fast input register by an explicit assignment in Quartus 13. But the compensation problem will probably persist.