Occasional Contributor
Super ContributorI'm not sure why you have this:
set_clock_groups -asynchronous -group [get_clocks {clk_ddr_virtual clk_ddr_input}]
It's not needed and may be what the tool is complaining about.
If this is a DDR input, why do you have the multicycle exceptions? There's no situation where multicycle is needed on a DDR input.
And is this same edge or opposite edge transfer? If it's same edge transfer, your false paths are incorrect. With same edge transfer, you want to "cut" opposite edge analysis, so the setup false paths should be rise_from/fall_to and fall_from/rise_to and the hold false paths should be rise_from/rise_to and fall_from/fall_to.
Occasional Contributor@sstrell This is an opposite edge transfer. Therefore the constraints are written this way. At least from what I could gather from AN433. But this note is really confusing for me.
But i never understood, why the transmission works when the sender delays (not advances) the clock signal by 90 degrees.
