Honored Contributor
Honored ContributorIn general, you might want to start a new post. Since this one is from last March, nobody is going to see it. (I got an email because I had replied to it).
go to www.alterawiki.com and click on Popular Pages on the left. It should be about the 3rd one down. It covers this, but basically: -max should be 2ns and -min should be -0.2. (For the setup check, the data needs to get there before the latching clock. If you say the external delay is 2ns, then the FPGA's delay must be -2ns compared to the clock. Likewise on hold, the data must get there after the latch clock. If there's a -0.2ns delay, then the FPGA's delay must be +0.2ns to still be later than the clock.)
