Source-Synchronous I/F and sdc commmands

Complement my guide, and you automatically get help. :)

You're inverting the clock going off chip by inverting the inputs of the clock's altddio_out. Quartus/TimeQuest does not recognize this inversion, so when you put a create_generated_clock assignment on the output clock, you will have to add the -invert option.

You don't state if you're using a PLL. It doesn't matter much, but the constraints our slightly different. Basicall you will have:

1) create_clock on clock coming in.

2) derive_pll_clocks if using PLL.

3) create_generated_clock on output port sending clock going off chip. The -source will either be the output of the PLL or the input clock port(1). This will have a -invert option.

4) Two set_output_delay constraints on the data going out. The -clock will be the clock created in 3).

What this creates is a center-aligned clock going off-chip with the data. When you run report_timing -setup and report_timing -hold on the data output ports, you should see the setup relationship being half the clock period, and the hold relationship being a negative half clock cycle.

So let's say the clock rate is 10ns. Your setup will be 5ns and hold will be -5ns. From here you can change your set_output_delay constraints to cut into that. For example, if you increase the -max value to 2ns and the -min value to -2ns, that basically means there is +/-2ns of skew outside the FPGA, so the FPGA can skew the data by +/-3ns and still make timing.

Often the hardest part is this last part, because data sheets may not represent their numbers as skew, but as setup and hold, but they work quite similarly. If you made it this far, post what you have and what your analysis is.