Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHi Jason,
Ther are two things you might try. The first is to use the se_max_delay command. Something like: set_max_delay -from [get_ports addr*] -to [get_registers buss_ack] 3 I am not 100% if this will work, but give it a try. The second option is to first create a clock for the WRN input. The period is not that critical - make it 10 ns for now: create_clock -period 10 -name wrn_clk [get_ports WRN] Now use the set_input_delay -max command (the -max option constrains the setup time, which is waht you want). Set the selay to 10-3 = 7 ns. set_input_delay -clock { wrn_clk } -clock_fall -max 7 [get_ports addr*] This in effect tell TimeQuest that you have a setup time of 3ns on the address input relative to the falling edge of the WRN input. From your description I would say that it is the comparator that creates the D input of the buss_ack register that is the problem. You only have 3 ns for the address signals to be compared to the range (plus the clock latency, min the input latency). It is possible that setting the timing constraint is simply going to tell you you have a problem, but it may not necessarily fix it. You need to increase the clock latency or decrease the input delay of the address lines, through the comparator. Maybe also try to make the comparator as simple as possible - only use the lines that are actually required. This will lead to aliasing, but that may be acceptable. Regards, Niki