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Altera_Forum
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15 years ago

Source synchronous constraints for both edges in TimeQuest

I've been working my way through the tutorials and Rysc's document. Unfortunately, the waveforms don't match what I'd expect. I thought I'd see the min-rise output delays from the rising edge of the launch clock to the rising edge of the latch clock, and from the falling edge of the launch clock to the falling edge of the latch clock. The rising edge is always the launch, which seems wrong.

Here's what I do: 

#  derive_clocks + correct periods.#  for each link, there is an external clock shifted -90 degrees
create_clock -name {clock_source} -period 10.000 -waveform { 0.000 5.000 } 
create_clock -name {l1_clk_in} -period 5.000 -waveform { 0.000 2.500 } }]
create_clock -name l1_tx_clk_0 -period 5.000 -waveform { 3.75 6.25 }
derive_pll_clocks
# HT output clock
create_generated_clock -source U_HT_CORE|U_HT_EC|htxtop_inst|ht_link_wrapper_I|CTLCADLO_OUT_SERDES_I|oserdes_altera_inst|altlvds_tx_component|auto_generated|lvds_tx_pll|clk -name l1_rx_clk_0 l1_clk_out
#  Cuts the clock output path; the tco can be unconstrained
set_false_path -from * -to }]
set_input_delay -min -1.000 -clock l1_tx_clk_0 } {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_ctrl_in}]]
set_input_delay -max 1.000 -clock l1_tx_clk_0 } {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_ctrl_in}]]
set_input_delay -min -1.000 -clock l1_tx_clk_0 } {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_ctrl_in}]] -clock_fall -add_delay
set_input_delay -max 1.000 -clock l1_tx_clk_0 } {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_cad_in} {l1_ctrl_in}]] -clock_fall -add_delay
set_output_delay -min 0.400 -clock l1_rx_clk_0 } {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_ctrl_out}]]
set_output_delay -max 1.200 -clock l1_rx_clk_0 } {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_ctrl_out}]]
set_output_delay -min 0.400 -clock l1_rx_clk_0 } {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_ctrl_out}]] -clock_fall -add_delay
set_output_delay -max 1.200 -clock l1_rx_clk_0 } {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_cad_out} {l1_ctrl_out}]] -clock_fall -add_delay
When I try the reports 

# report_timing -from_clock { U_HT_CORE|U_HT_EC|htxtop_inst|ht_link_wrapper_I|CTLCADLO_OUT_SERDES_I|oserdes_altera_inst|altlvds_tx_component|auto_generated|lvds_tx_pll|clk } -to_clock { l1_rx_clk_0 } -from {xd1000_ht_core:U_HT_CORE|ht_ec:U_HT_EC|ht_link:htxtop_inst|ht_link_wrapper_200:ht_link_wrapper_I|oserdes_altera9_buf:CTLCADLO_OUT_SERDES_I|oserdes_altera9_logic:oserdes_altera_inst|altlvds_tx:altlvds_tx_component|oserdes_altera9_logic_lvds_tx:auto_generated|oserdes_altera9_logic_ddio_out:ddio_out|ddio_outa_0~data_in_reg} -to {l1_cad_out} -hold -npaths 100 -detail full_path -panel_name {Report hold Timing}# report_timing -from_clock { U_HT_CORE|U_HT_EC|htxtop_inst|ht_link_wrapper_I|CTLCADLO_OUT_SERDES_I|oserdes_altera_inst|altlvds_tx_component|auto_generated|lvds_tx_pll|clk } -to_clock { l1_rx_clk_0 } -from {xd1000_ht_core:U_HT_CORE|ht_ec:U_HT_EC|ht_link:htxtop_inst|ht_link_wrapper_200:ht_link_wrapper_I|oserdes_altera9_buf:CTLCADLO_OUT_SERDES_I|oserdes_altera9_logic:oserdes_altera_inst|altlvds_tx:altlvds_tx_component|oserdes_altera9_logic_lvds_tx:auto_generated|oserdes_altera9_logic_ddio_out:ddio_out|ddio_outa_0~data_in_reg} -to {l1_cad_out} -setup -npaths 100 -detail full_path -panel_name {Report setup Timing}

The first hold relationship is -1.25 ns, which is what I expected, but the next one is -3.75 ns, which is too long. The same is true for setup, but the sign is switched.

My question is either:

- How can I constrain the correct edges?

or

- Why is this behavior correct?

Thanks,

Myles

12 Replies

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    I recommend against cutting rise->fall or whatever transfers.

    ...

    If done correctly, these false paths don't hurt anything. But if done incorrectly, which I have see many times, the user cuts the inside path and has incorrect timing analysis. I guess I'm saying they don't really help, but have the potential to hurt your design.

    --- Quote End ---

    I see your point. I'll remove the false path statements. I was trying to make the output simpler.

    --- Quote Start ---

    My major concern is that your output delays are skewed, i.e. 0.4 and 1.2. Is your PLL phase-shifting the clock going out by 90 degrees?

    --- Quote End ---

    Yes it's shifting it.

    I think this is probably due to my misunderstanding of the data sheet. I was looking at the clock output skew values, and didn't realize that it included the phase shift.

    I guess I should have been looking at the minimum and maximum setup and hold times instead.

    So if I have maximum setup and hold times of 175 ns, does that mean that those become the output delays?

    Thanks,

    Myles
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    I've been working my way through the tutorials and Rysc's document.

    --- Quote End ---

    Rysc,

    I appreciate the time you put into the User Guide. I found it very useful. I have some constructive feedback for you, but I can't send you a private message. If you're interested, let me know how you'd like to receive it.

    Thanks,

    Myles