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I recommend against cutting rise->fall or whatever transfers.
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If done correctly, these false paths don't hurt anything. But if done incorrectly, which I have see many times, the user cuts the inside path and has incorrect timing analysis. I guess I'm saying they don't really help, but have the potential to hurt your design.
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I see your point. I'll remove the false path statements. I was trying to make the output simpler.
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My major concern is that your output delays are skewed, i.e. 0.4 and 1.2. Is your PLL phase-shifting the clock going out by 90 degrees?
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Yes it's shifting it.
I think this is probably due to my misunderstanding of the data sheet. I was looking at the clock output skew values, and didn't realize that it included the phase shift.
I guess I should have been looking at the minimum and maximum setup and hold times instead.
So if I have maximum setup and hold times of 175 ns, does that mean that those become the output delays?
Thanks,
Myles
Honored Contributor
