Source-Synchoronous Interface: Edge Aligned SDR Clock constraint

Hi.

I am designing using a Cypress FX3 device (CYUSB3014-BZXC) and a Cyclone IV FPGA (EP4CE115F29C8). The FPGA has a external 50 MHz oscillator. The design should run @ 100 MHz. To do this I have an internal PLL to generate it.

The FX3 device has a 32 bits source synchronous interface running @100MHz clock coming from the FPGA. The FX3 device receive the data center-aligned.

As guidance for the port name I has the following ones:

module SLAVE_FIFO_STREAM_IN(
    input              CLOCK_50,       //input clp 50 Mhz
    inout            FX3_DQ,          //data bus
    output                FX3_faddr,       //output fifo address  
    output             FX3_slrd,         //output read select
    output             FX3_slwr,         //output write select
    input              FX3_flaga,       //full flag
    input              FX3_flagb,       //partial full flag
        input              FX3_flagc,       //empty flag
    input              FX3_flagd,      //empty partial flag
    output             FX3_sloe,       //output output enable select
    output             FX3_CLK,       //output clk 100 Mhz and 180 phase shift
    output             FX3_slcs,       //output chip select
    output             FX3_pktend,  //output pkt end
    output                FX3_PMODE,
    output             FX3_RESET,
    output             FX3_PMODE_2 //used for debugging
);

I already set the next into my design:

1) An altddio_out_component to shift the out clock 180° (Connected the datain_h(1'b0) and datain_l(1'b1) to make it)

2) I already set the output parallel interface as: "set_instance_assignment -name FAST_OUTPUT_REGISTER ON"

3) My SDC constraints are the next ones:

set_time_format -unit ns -decimal_places 3
# **************************************************************#  Create Clock# **************************************************************
create_clock -name CLOCK_50M -period 20.000 
create_generated_clock 
 -name CLOCK_100M 
 -multiply_by 2 
 -source }] 
  }] 
  # **************************************************************#  Create Generated Clock# **************************************************************
#  Put a generated clock on output clock port to be referenced by set_output_delay constraints.  Note the -invert option, which says the clock is being inverted on the way out.  This is important#  since Quartus doesn't recognize the DDR output with VCC/GND switched as inverting the clock
create_generated_clock -source }] -name CLOCK_FX3  -invert
set_false_path -to 
# Constrain the PLL automatically
derive_pll_clocks -create_base_clocks
# **************************************************************#  Set Clock Uncertainty# **************************************************************
derive_clock_uncertainty
# ################################################################################ Parameters# ###############################################################################
#  Specify the maximum external clock delay to the FPGA
set FX3_CLKs_max 0#  Specify the minimum external clock delay to the FPGA
set FX3_CLKs_min 0#  Specify the maximum external clock delay to the external device
set FX3_CLKd_max 0#  Specify the minimum external clock delay to the external device
set FX3_CLKd_min 0#  Specify the maximum setup time of the external device
set FX3_tSU 2#  Specify the minimum setup time of the external device
set FX3_tH 0.5#  Specify the maximum board delay
set FX3_BD_max 0#  Specify the minimum board delay
set FX3_BD_min 0
#  Specify the maximum clock-to-out of the external device
set FX3_tCO_max 9#  Specify the minimum clock-to-out of the external device
set FX3_tCO_min 2
# ################################################################################ Output constraints# ###############################################################################        
set_output_delay -clock CLOCK_FX3 -max  
set_output_delay -clock CLOCK_FX3 -min   -add_delay
# ################################################################################ Input constraints# ###############################################################################
set_input_delay -clock CLOCK_FX3 -max  
set_input_delay -clock CLOCK_FX3 -min                    

I have been reviewing the Timequest guides provided in the AlteraWiki and the corresponding manuals. But I cannot evacuate the next doubt:

As the design has a clock offset of 180° between the launch and the latch clock, (relative to the outputs to the device) I do not know which is the right way to constraint this. I should use a set_multicycle_path command? The design has a synchonizer between the register coming from the external device, but I do not know how tell this to Timequest.

I attached a zipped file for the design if this is easier to understand.

Thanks in advance.

Franco