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Altera_Forum's avatar
Altera_Forum
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8 years ago

Sorry! The Quartus Prime software quit unexpectedly.

When you have vhdl with an error like: data(to_integer(index) to to_integer(index)+15)<="101010101010101"; (the right side is one bit short) Quartus stops but does not tell you why. I contac...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi

I don't know what version of quartus you are using.

But in quartus 17, it says explicitly that the expression on the right side must have 16 elements.

In verilog, this kind of assignment (the right side is lower/greater then the the left side) is allowed , although quartus reports some warnings related to truncation.

--kais--