Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi,
I don't think they are useless. AFAIK the clock modules are generated when you are using different clocks in your sopc builder design. I think they are needed for the clock domain crossing. The burst modules are generated when you enable cache bursting (Nios processor -> caches and memory Interfaces tab). There will be one burst module for each connection between the data/instruction master and a component. You can avoid this by disabling cache bursting. But if you are using SDRAM/DDRx you will probably see a performance penalty.