Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

SOPC Builder 7.1 Problem with New Components

Hi,

In SOPC Builder 7.1, I am trying to create a component to connect to an off-chip SRAM. I use the "Create new component..." wizard in SOPC Builder.

Everything seems fine. I set the interface to "Avalon Tristate Slave", define all the signals (data, addr, oe_n, etc) and their sizes and directions, define the name, and then hit finish.

The new component appears in the list. I add it to the system, but then run into a problem when I try to connect it to the tri-state bridge. There is a Flash (CFI) on the same physical off-chip bus. It seems that in SOPC 7.1 you need to set the tri-state bridge component to tell it which signals in the components connected to it are shared.

However, when I double click on the tri-state bridge component to edit it, a Java NullPointerException is thrown. Disconnecting my custom SRAM component makes the error go away.

Further, whenever I try to re-edit my custom component, it always comes up with the data signal as an input, even though it was properly set to bidir.

I have seen the posts about adding the folder to the Global Libraries list, but this does nothing.

Anyone else having similar problems with SOPC 7.1? Any ideas to fix it?

Here is the .tcl script that SOPC 7.1 creates to define the custom component:

# TCL File Generated by Component Editor on:

# Sun Jun 10 03:32:15 PDT 2007

# DO NOT MODIFY

# Blackbox -- The top level is not based on an HDL file

set_source_file ""

set_module "idt71v416"

set_module_description ""

set_module_property instantiateInSystemModule false

set_module_property version "1.0"

set_module_property group "User Logic"

set_module_property editable true

# Module parameters

# Clock Interface global_signals_clock

add_clock_interface "global_signals_clock"

set_interface_property "global_signals_clock" "externallyDriven" "false"

set_interface_property "global_signals_clock" "clockRateKnown" "false"

set_interface_property "global_signals_clock" "clockRate" "0"

# Ports in interface global_signals_clock

add_port_to_interface "global_signals_clock" "clk" "clk"

set_port_direction_and_width "clk" "input" 1

add_port_to_interface "global_signals_clock" "reset_n" "reset_n"

set_port_direction_and_width "reset_n" "input" 1

# Interface avalon_tristate_slave_0

add_interface "avalon_tristate_slave_0" "avalon_tristate" "slave" "global_signals_clock"

set_interface_property "avalon_tristate_slave_0" "isNonVolatileStorage" "false"

set_interface_property "avalon_tristate_slave_0" "burstOnBurstBoundariesOnly" "false"

set_interface_property "avalon_tristate_slave_0" "transparentBridge" "false"

set_interface_property "avalon_tristate_slave_0" "readLatency" "0"

set_interface_property "avalon_tristate_slave_0" "readWaitStates" "1"

set_interface_property "avalon_tristate_slave_0" "isFlash" "false"

set_interface_property "avalon_tristate_slave_0" "holdTime" "0"

set_interface_property "avalon_tristate_slave_0" "printableDevice" "false"

set_interface_property "avalon_tristate_slave_0" "registerIncomingSignals" "false"

set_interface_property "avalon_tristate_slave_0" "readWaitTime" "1"

set_interface_property "avalon_tristate_slave_0" "setupTime" "0"

set_interface_property "avalon_tristate_slave_0" "addressGroup" "0"

set_interface_property "avalon_tristate_slave_0" "interleaveBursts" "false"

set_interface_property "avalon_tristate_slave_0" "addressAlignment" "DYNAMIC"

set_interface_property "avalon_tristate_slave_0" "isBigEndian" "false"

set_interface_property "avalon_tristate_slave_0" "writeLatency" "0"

set_interface_property "avalon_tristate_slave_0" "writeWaitTime" "1"

set_interface_property "avalon_tristate_slave_0" "timingUnits" "Cycles"

set_interface_property "avalon_tristate_slave_0" "minimumUninterruptedRunLength" "1"

set_interface_property "avalon_tristate_slave_0" "registerOutgoingSignals" "false"

set_interface_property "avalon_tristate_slave_0" "addressSpan" "524288"

set_interface_property "avalon_tristate_slave_0" "activeCSThroughReadLatency" "false"

set_interface_property "avalon_tristate_slave_0" "isMemoryDevice" "true"

set_interface_property "avalon_tristate_slave_0" "alwaysBurstMaxBurst" "false"

set_interface_property "avalon_tristate_slave_0" "linewrapBursts" "false"

set_interface_property "avalon_tristate_slave_0" "writeWaitStates" "1"

set_interface_property "avalon_tristate_slave_0" "maximumPendingReadTransactions" "0"

set_interface_property "avalon_tristate_slave_0" "wellBehavedWaitrequest" "false"

# Ports in interface avalon_tristate_slave_0

add_port_to_interface "avalon_tristate_slave_0" "data" "data"

set_port_direction_and_width "data" "bidir" 16

add_port_to_interface "avalon_tristate_slave_0" "addr" "address"

set_port_direction_and_width "addr" "input" 18

add_port_to_interface "avalon_tristate_slave_0" "cs_n" "chipselect_n"

set_port_direction_and_width "cs_n" "input" 1

add_port_to_interface "avalon_tristate_slave_0" "oe_n" "read_n"

set_port_direction_and_width "oe_n" "input" 1

add_port_to_interface "avalon_tristate_slave_0" "we_n" "write_n"

set_port_direction_and_width "we_n" "input" 1

add_port_to_interface "avalon_tristate_slave_0" "be_n" "byteenable_n"

set_port_direction_and_width "be_n" "input" 2

22 Replies