Honored Contributor
Honored ContributorOkay here we go...
1 - There is no interface to user logic component anymore. The reason is that it's trivial to create your own. Basically all you do is use the "New Component Wizard" from within SoPC builder to create your new component. You just create the appropriate signals (either manually or using a template) and configure the interfaces appropriately (timing, latency, etc.). Then because the component is not based on HDL, when you create an instance of the component in your SoPC system, it's signals will automatically be exported to the top-level where you can connect them to your user logic. Recommended reading: http://www.altera.com/literature/lit-sop.jsp However, if this seems daunting I've attached a generic component that is based on HDL that exports the avalon signals out of the system. You can use it if it meets your needs. 2 - The macro found in system.h "<COMPONENT_NAME>_SPAN" (in your case MY_INTERFACE_SPAN) is merely a macro that can be used to determine how much address space is occupied by the component on the avalon bus. It is rarely used. The other macro <COMPONENT_NAME>_BASE (in your case MY_INTERFACE_BASE) refers to the base address of the component on the NIOS processor's bus. This macro is very important as it tells you where to access your component on the bus. As far as accessing the component, you've been given it's address on the bus so you know where it is and in theory you can access it however you want. However, Altera provides the IOWR and IORD macros specifically for acessing your hardware components. Please see page 9-4 of this document: http://www.altera.com/literature/hb/nios2/n2sw_nii5v2.pdf Jake
