Single multiplier takes up a whole DSP block for

According to my observation, Quartus uses all available DSP block before it starts packing multipliers. See same-topic discussion at Edaboard

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity test1 is
generic(
 n : integer := 50;
 w : integer := 18
);
port(
	clk	: in STD_LOGIC;
	sel	: in integer range 0 to n-1;
	ax	: in signed(w-1 downto 0);
	bx	: in signed(w-1 downto 0);
	cx	: out SIGNED(2*w-1 downto 0)
);
end test1;
architecture rtl of test1 is
type ar18 is array(0 to n-1) of signed(w-1 downto 0);
type ar36 is array(0 to n-1) of signed(2*w-1 downto 0);
signal ar : ar18;
signal br : ar18;
signal cr : ar36;
begin
process (clk)
	begin
		if rising_edge(clk) then
			for i in 0 to n-1 loop
				cr(i) <= ar(i)*br(i);
				if i = sel then
					ar(i) <= ax;
					br(i) <= bx;
					cx <= cr(i);
				end if;
			end loop;
		end if;
	end process;
end rtl