I have understand how the ROM works and how to interface it. Now it is the SIN function that gives me trouble.
I have this code:
-- Quartus II VHDL Template
-- Dual-Port ROM
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE ieee.std_logic_arith.all;
USE ieee.math_real.all;
entity dual_port_rom is
generic
(
DATA_WIDTH : natural := 14;
ADDR_WIDTH : natural := 4096
);
port
(
clk : in std_logic;
addr_a : in integer range 0 to 2**ADDR_WIDTH - 1;
q_a : out std_logic_vector((DATA_WIDTH -1) downto 0)
);
end entity;
architecture rtl of dual_port_rom is
subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
TYPE ROM IS ARRAY((ADDR_WIDTH-1) downto 0) OF word_t;
FUNCTION INIT_ROM RETURN ROM IS
VARIABLE romvar: ROM;
VARIABLE x: REAL;
begin
for I in 0 TO 2**ADDR_WIDTH-1 loop
x:= SIN(real(i)*MATH_PI/real(ADDR_WIDTH-1));
romvar(i):= std_logic_vector(to_unsigned(x*real(ADDR_WIDTH-1),DATA_WIDTH));
end loop;
return romvar;
end;
-- Declare the ROM signal and specify a default value. Quartus II
-- will create a memory initialization file (.mif) based on the
-- default value.
signal rom : memory_t := romvar;
begin
process(clk)
begin
if(rising_edge(clk)) then
q_a <= rom(addr_a);
end if;
end process;
end rtl;
It is the same code that i posted before except that I have change to bit vectors instead of integers. But I get an error on the line:
romvar(i):= std_logic_vector(to_unsigned(x*real(ADDR_WIDTH-1),DATA_WIDTH));
It say it can't determine definition of operator ""*"".
I have tried to do some sort of workaround but I can't get it to work:
Does anybody knows why?