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Altera_Forum's avatar
Altera_Forum
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18 years ago

Simulator assignments

Hi, I try to simulate a design with the QuartusII simulator. Some of the signals are however synthesised away. I connect the signals to output pins and use the "Implement as Output of Logic Cell",...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I have tried to put output pins on the lower-level blocks and set the Preserve Fan-out Free Register Node logic option without any luck. I also tried to look in the RTL viewer for the signal and assign the same option, but still the signals are no where to be found in the simulator.

I can only see them if I set the search option to "All name", but when I run the simulator they keep disappearing.

Any thoughts?