Simulator accuracy

Hello!

Thanks again, Rysc!

Well, I think I use the classic time analyser because I did not fill in some constraints by myself. . .

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What's the clocking scheme? If you're board level clock that feeds the FPGA also feeds the ADC, then you've got a pretty standard analysis. If the board clock is laid out for low clock skew, then you've got a single period for the ADC to get data off chip, across the board, and into the FPGA. If there is skew, you need to account for that. If your ADC sends a clock to the FPGA alongside the data, it gets more complicated. I believe there is a Source-Synchronous App Note for TimeQuest that was put on the web. That's close to being as complicated as it gets, but usually isn't too bad.

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Now, it gets a little too deep . . . Maybe I have to think about that a little until I understand what you mean by this. . . .

As far as I can tell you, I use the devided clock through a FPGA pin to feed the ADC. Then I wait two main clock cycles and then I fetch the data from the input pins of the FPGA who are connected to the output pins of the ADC. As I said, this works pretty fine for my project . . .

Maik