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Altera_Forum
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18 years ago

Simulator accuracy

Hello! I am designing with Quartus II Software for about 2 months now. First my focus was on learning VHDL. In the meantime, my design gets pretty complex and now I wonder, how accurate the Sim...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello Rysc!

Thank you for you answer. It is very informative!

In the beginning of my efforts for my current project (which is also my first VHDL/FPGA project) I ask myself (and in a german forum) if it would be better to use a PLL. At that time my understanding of PLLs was very limited, and everybody told me, that it is no problem to devide (or as you say 'register') the main clock.

I use the divided clock to drive a ADC at 25 MHz. Up to now, it works very good and I have no problems because I allways try to comprise all timinginformations,I have (out of the datasheets of my components and from the simulator results), into my design.

Now, as the project gets more and more complex, I have some (I admit: combinative) signals that are just stable very close to the clock edge, when the result will be registered (2ns). Now I wonder, if I have to face massiv problems in the real world, without probably knowing, why.

Greets

Maik