Simulation/Testbench files in Quartus-II

For RTL simulation files (.v or .vhd), Quartus cannot distinguish between synthesis and simulation files other than when you try to synthesize a simulation file that has commands that can't be synthesized.

All you need to do in Quartus is add the synthesis files in the project settings, setting one of them as the top-level entity. Any files not in the settings, even if it is in your project directory, will not be used for synthesis.